1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor chip underfills and methods of making the same.
2. Description of the Related Art
Many types of conventional packaged integrated circuits consist of a semiconductor chip flip-chip mounted to a package substrate. Electrical interconnections between the semiconductor chip and a package substrate are provided by a plurality of solder bumps. The materials used for the semiconductor chip, the solder bumps, and the package substrate are selected for certain desirable characteristics. For example, the semiconductor chip is usually composed of silicon or a laminate of silicon and silicon dioxide. Silicon is selected for its advantageous semiconductor properties. Solder is selected as a bump material due to its electrical conductivity and easy thermal reflow properties. Conventional organic package substrates are frequently composed of alternating layers of epoxy resins. The layers are relatively inexpensive to manufacture. Although these various materials provide certain favorable characteristics, there is a penalty for using disparate materials.
The use of dissimilar materials results in the semiconductor chip and the package substrate having rather different coefficients of thermal expansion (CTE). Indeed, the CTE of the substrate may be larger than the CTE of the semiconductor chip by a factor of ten or more. The differences in CTE between a semiconductor chip and the package substrate can, if not compensated for, impose tremendous stresses on the solder bumps. If the stresses are too large, bump failure and delamination can occur.
To compensate for differences in CTE between the semiconductor chip and the package substrate, manufacturers have, for some time, placed an underfill layer between the semiconductor chip and the package substrate. The conventional underfill is designed to have a CTE that falls somewhere in between the CTE of the chip and the CTE of the substrate. In a conventional process, the chip is mounted to the substrate and a solder reflow is performed. Next, an epoxy resin that includes a collection of filler particles of silica is deposited at the edges of a semiconductor chip after the chip is preliminarily coupled to the substrate. Surface tension forces tend to draw the deposited underfill material into the voids between the semiconductor chip and the substrate. A subsequent thermal cure sets the underfill material.
Conventional underfill materials have a bulk modulus and CTE that does not vary with depth. Accordingly, the bulk modulus at the top of the underfill layer is substantially the same as the bulk modulus at the bottom of the same layer. Unfortunately, the conventional underfill material may still present a rather abrupt difference in CTE relative to both the chip and the substrate.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.